1. Technical Field
The present disclosure relates to a semiconductor device.
2. Description of the Related Art
As a scaling technology to increase the density of a semiconductor device, a multi-gate transistor including a fin-shaped or nanowire-shaped, multi-channel active pattern (or silicon body) formed on a substrate and a gate formed on a surface of the multi-channel active pattern has been suggested. Since the multi-gate transistor includes a three-dimensional channel, the scaling of the transistor may be facilitated. In addition, current control capability may be improved even without an increase in a gate length of the multi-gate transistor. Moreover, a short channel effect (SCE) in which the potential of a channel region is affected by a drain voltage may be effectively suppressed.